Recent advancements in the electronics industry, especially with personal computers (PC), mobile phones, and personal data assistants (PDA), have triggered a need for light, compact, and multi-functional power systems that can process large amounts of data quickly. These advancements have also triggered a reduction in the size of semiconductor chips and the packaging used for theses chips.
The semiconductor chips typically have conductive pads formed at the top surface of the silicon substrate containing the IC. Wire bonding is used to connect the conductive pads on the substrate to corresponding pads on a package substrate. The increasing complexity of the circuitry in the IC has required the conductive pads to be formed closer together. With the bond pads narrower, the length of the wire (in the wire bonding) needs to be longer and width narrower which unfortunately induces a greater amount of inductance and thereby reduces the speed of the circuitry.
One type of packaging that has been recently used is wafer-level chip size packaging (WLCSP). See, for example, U.S. Pat. Nos. 6,187,615 and 6,287,893, the disclosures of which are incorporated herein by reference.
In general, to fabricate WLCSP, a wafer is processed and then packaged by a photolithography process and a sputtering process. This method is easier than general packaging processes that use die bonding, wire bonding, and molding. Processes for WLCSP also have other advantages when compared to general packaging processes. First, it is possible to make solder bumps for all chips formed on a wafer at a single time. Second, a wafer-level test on the operation of each semiconductor chip is possible during WLSCP processes. For these—and other reasons—WLCSP can be fabricated at a lower cost than general packaging.
FIGS. 1-3 illustrate several known wafer-level chip scale packages. As shown in FIG. 1, chip pads 40 are formed of a metal such as aluminum on a silicon substrate 5. A passivation layer 10 is formed to expose a portion of each of the chip pads 40 on the silicon substrate 5 while protecting the remainder of the silicon substrate 5. A first insulating layer 15 is formed over the passivation layer 10 and then a re-distribution line (RDL) pattern 20 (which re-distributes electrical signals from the bond pad 40 to solder bump 35) is formed over portions of the first insulating layer 15 and the exposed chip pads 40. A second insulating layer 25 is formed on portions of the RDL pattern 20 while leaving portions of the RDL pattern 20 exposed. Under bump metals (UBM) 30 are formed between solder bumps 35 and the exposed portions of the RDL pattern 20. The RDL pattern 20 contains inclined portions on the first insulating layer 15 near the chip pads 40. In these areas, short circuits can occur and the pattern 20 can crack and deform in these areas due to stresses.
As depicted in FIG. 2, package 50 contains an RDL pattern 54 that adheres to a solder connection 52 in a cylindrical band. Such a configuration has several disadvantages. First, the contact area between the RDL pattern 54 and the solder connection 52 is minimal, thereby deteriorating the electrical characteristics between them. Second, short circuits may occur due to the stresses in the contact surface between the RDL pattern 54 and the solder connection 52. Third, the solder connection 52—which is connected with a solder bump 58 formed on a chip pad 56—is exposed to the outside of the package 50, i.e., to air. Thus, there is a higher possibility that moisture penetrates into the solder connection 52 and decreases the reliability of the solder connection 52. Fourth, the package 50 is completed only by carrying out many processing steps and, therefore, manufacturing costs are high.
As shown in FIG. 3, package 60 contains a RDL pattern 76 that is electrically connected with a chip pad 72 via a connection bump 74. The RDL pattern 76 is, however, inclined on the connection bump 74, causing cracks therein due to stresses as described above. As well, the connection bump 74 is made by a plating process and is formed of aluminum, copper, silver, or an alloy thereof. Accordingly, the package 60 is not easy to manufacture.
Other problems exist with conventional WLSCP. Often, such packaging uses UMB (i.e., layer 30 in FIG. 1) and two insulating layers (i.e., layers 15 and 25 in FIG. 1) that are made of polymeric materials such as polyimide and benzocyclobutene (BCB). Such structures are complicated to manufacture and very expensive because of materials and equipment used. As well, the coefficient of thermal expansion (CTE) between the various layers can induce thermal stresses into the ICs and damage the ICs during high temperature curing of these polymeric materials.
As well, conventional packaging methods have used a conductive film or paste in flip chip packaging. See, for example, U.S. Pat. Nos. 5,9494,142, 6,509,634, and 6,518,097, the disclosures of which are incorporated herein by reference. Generally, these methods used a gold bump on a silicon die and then bonded it to a substrate (usually ceramic) using the conductive film or paste using ultrasonic bonding. Such methods, however, suffer from a high cost and poor reliability.
Further, the trend of semiconductor packaging including WL-CSP is to use smaller, lighter and thinner form factors that enable the manufacture of smaller semiconductor devices. The use of smaller form factors in a WL-CSP packaging with small die and large I/O, however, could result in manufacturing challenges. One of these challenges is the alignment of solder balls on a die 501 (i.e., small pitch) to the alignment of lands/pads on the printed circuit board 502 (i.e. large pitch) as illustrated in FIG. 31.